Scratchpad memory

Scratchpad anamnesis (SPM), additionally accepted as scratchpad, scatchpad RAM or bounded abundance in computer terminology, is a accelerated centralized anamnesis acclimated for acting accumulator of calculations, data, and added assignment in progress. In advertence to a chip ("CPU"), scratchpad refers to a appropriate accelerated anamnesis ambit acclimated to authority baby items of abstracts for accelerated retrieval.

It can be advised agnate to the L1 accumulation in that it is the abutting abutting anamnesis to the ALU afterwards the centralized registers, with absolute instructions to move abstracts from and to capital memory, generally application DMA-based abstracts transfer. In adverse with a arrangement that uses caches, a arrangement with scratchpads is a arrangement with Non-Uniform Anamnesis Admission latencies, because the anamnesis admission latencies to the altered scratchpads and the capital anamnesis vary. Another aberration with a arrangement that employs caches is that a scratchpad frequently does not accommodate a archetype of abstracts that is additionally stored in the capital memory.

Scratchpads are active for description of caching logic, and to agreement a assemblage can assignment after capital anamnesis altercation in a arrangement employing assorted processors, abnormally in multiprocessor system-on-chip for anchored systems. They are mostly ill-fitted for autumn acting after-effects (as it would be begin in the CPU stack) that about wouldn't charge to consistently be committing to the capital memory; about back fed by DMA, they can additionally be acclimated in abode of a accumulation for apery the accompaniment of slower capital memory. The aforementioned issues of belt of advertence administer in affiliation to ability of use; although some systems acquiesce strided DMA to admission ellipsoidal abstracts sets. Another aberration is that scratchpads are absolutely manipulated by applications.

Scratchpads are not acclimated in boilerplate desktop processors area generality is appropriate for bequestcomputer application to run from bearing to generation, in which the accessible on-chip anamnesis admeasurement may change. They are more good implemented in anchored systems, special-purpose processors and bold consoles, area chips are generally bogus as MPSoC, and areacomputer application is generally acquainted to one accouterments configuration

Examples of use

The Cyrix 6x86, the alone x86-compatible desktop processor to absorb a committed Scratchpad.

SuperH, acclimated in Sega's consoles, could lock cachelines to an abode alfresco of capital anamnesis for use as a Scratchpad.

The Sony PS1's R3000 had a Scratchpad instead of an L1 cache. It was accessible to abode the CPU assemblage here, an archetype of the acting workspace usage.

Sony's PS2 Emotion Engine active a 16KiB Scratchpad, to and from which DMA transfers could be issued to its GS, and capital memory.

The Cell's SPEs are belted absolutely to alive in their "local-store", relying on DMA for transfers from/to capital anamnesis and amid bounded stores, abundant like a Scratchpad. In this regard, added account is acquired from the abridgement of accouterments to analysis and amend adherence amid assorted caches: the architecture takes advantage of the acceptance that anniversary processor's workspace is abstracted and private. It is accepted this account will become added apparent as the cardinal of processors scales into the "many-core" future.

Many added processors acquiesce L1 accumulation curve to be locked.

Most DSPs use a Scratchpad. Many accomplished 3D accelerators and bold consoles (including the PS2) accept acclimated DSPs for acme transformations. This differs with the beck based access of avant-garde GPUs which accept added in accepted with a CPU cache's functions.

NVIDIA's 8800 GPU active beneath CUDA provides 16KiB of Scratchpad per thread-bundle back actuality acclimated for gpgpu tasks.

Ageia's PhysX dent utilizes Scratchpad RAM in a address agnate to the Cell; its approach states that a accumulation bureaucracy is of beneath use thancomputer application managed physics and blow calculations. These memories are additionally banked and a about-face manages transfers amid them

Cache control vs Scratchpads

Many architectures such as PowerPC attack to abstain the charge for cacheline locking or scratchpads through the use of accumulation ascendancy instructions. Marking an breadth of anamnesis with "Data Accumulation Block: Zero" (allocating a band but ambience its capacity to aught instead of loading from capital memory) and auctioning it afterwards use ('Data Accumulation Block: Invalidate', signaling that capital anamnesis needn't accept any adapted data) the accumulation is fabricated to behave as a scratchpad. Generality is maintained in that these are hints and the basal accouterments will action accurately behindhand of absolute accumulation size

Shared L2 vs Cell local stores

Regarding interprocessor advice in a multicore setup, there are similarities amid the Cell's inter-localstore DMA and a Aggregate L2 accumulation bureaucracy as in the Intel Amount 2 Duo or the Xbox 360's custom powerPC: the L2 accumulation allows processors to allotment after-effects after those after-effects accepting to be committed to capital memory. This can be an advantage area the alive set for an algorithm encompasses the absoluteness of the L2 cache. However, back a affairs is accounting to booty advantage of inter-localstore DMA, the Cell has the account of each-other-Local-Store confined the purpose of BOTH the clandestine workspace for a distinct processor AND the point of administration amid processors; i.e., the added Local Stores are on a agnate basement beheld from one processor as the aggregate L2 accumulation in a accepted chip. The tradeoff is that of anamnesis ashen in buffering and programming complication for synchronization, admitting this would be agnate to precached pages in a accepted chip. Domains area application this adequacy is able include:

Pipeline processing (where one achieves the aforementioned aftereffect as accretion the L1 cache's admeasurement by agreeable one job into abate chunks).

Extending the alive set, e.g., a candied atom for a absorb array area the abstracts fits aural 8x256KiB

Aggregate cipher uploading, like loading a allotment of cipher to one SPU, afresh archetype it from there to the others to abstain hitting the capital anamnesis again.

It would be accessible for a accepted processor to accretion agnate advantages with cache-control instructions, for example, acceptance the prefetching to the L1 bypassing the L2, or an boot adumbration that signaled a alteration from L1 to L2 but not committing to capital memory; however, at present no systems action this adequacy in a accessible anatomy and such instructions in aftereffect should mirror absolute alteration of abstracts amid accumulation areas acclimated by anniversary core.